GONZALEZ, Eduardo J. -------------- Patent Agent

 Tel.: +1 (202) 299-7895                             Addr.: 5103 Yuma Ct. N.W. Washington, DC 20016 USA




    o   College of Professional Studies: Washington, DC

    o   Master of Professional Studies, Paralegal Studies (GPA 4.0)


    o   Jacobs School of Engineering: San Diego, CA

    o   Masters of Engineering, Electrical & Computer Engineering (GPA 3.5)

·        UNIVERSITY OF VIRGINIA (May 2001)

    o   School of Engineering and Applied Science: Charlottesville, VA

    o   Bachelor of Science, Electrical Engineering; Computer Science Minor (GPA 3.4)


    o   Masters of Divinity, Dominican House of Studies (1 Semester only: 4 Philosophy & 1 Latin Courses)

Security Clearance – Secret (expired in 2010)

Employment History


Muir Patent Law

February – Present 2015

Patent Agent


Juneau & Mitchell and Verstegen & Fobe

May-June 2014 and October 2014



Takedo Panacea Ltd.

June 2009 – September 2014



Petroport SA, AgroIndustrial del Baru SA, H&M Engineering Inc, & PFIC

October 2009 – March 2013

Maintenance Engineer, Co-manager, Consultant, & Clerk


ViaSat, Inc.

July 2003 – August 2009

PL/HW/Test/Lead Engineer & PM


University of California, San Diego and Qualcomm CDMA Technologies (QCT)

June 2002 – December 2002 and January 2003 – June 2003

Research Assistant and VLSI Intern


Raytheon Systems Company and Hughes Network Systems

May 1999 – August 1999 and May 2000 – August 2000 and June 2001 – November 2001

Software Aide and Electrical Engineering Intern and VLSI Engineer

Applicable Experience


·         Muir Patent Law (February – Present 2015)

             o     Prosecution of Patents at the USPTO

·        Juneau & Mitchell, Verstegen & Fobe (May-June 2014, October 2014)

             o     Contact Eduardo for details

·        Takedo Panacea, Ltd. (Jun. 2009 – Present)

             o     Submitted a 53 page patent for a breakthrough chewing gum product that enables a “Zen”, meditative mental state, including a registered trademark
             o     Performed five (5) demonstration runs for Salviation Gum of varying success, altering the ingredients list each time to then send out samples to potential investors and distributors
             o     Performed extensive research, business planning, logistics preparation, petition planning, risk mitigation, and detailed descriptions of three products and two services, including the ongoing Business proposal for the upcoming, private "Nerveana" multi-modalistic Wellness Center 
             o     Created a 279 p. copyrighted document detailing business concepts, including philosophical rationale and financial analysis of the different products & services   

·        Petroport & Petrobunker, S.A. (Sep. 2012 – Mar. 2013)

             o     Assistant to all Engineering & Operations activities, especially Maintenance, while learning & utilizing all previously learned skills in Industrial, Mechanical, Electrical, and some Civil & Chemical Engineering
             o     Developed a yearly preventative maintenance plan for all equipment, including generators, fire extinguishing systems, pumps, various networks of tubes & valves, instruments, vehicles, trucks, landscaping, and the various building structures
             o     Technical support of the plant, including operational process areas and guiding the management of electro-mechanical equipment, according to the manufacturer's standards and engineering norms
             o     Solicited various purchase orders for materials & tools and helped supervise reactive maintenance tasks

·        AgroIndustrial del Barú, S.A. (Sep. 2011 – Sep. 2012)

             o     Operations and planning, apprecnticeship, and co-management of 400 acre Coffee farm, including the automatic wet/dry processing\
             o     Learned agricultural techniques of fertilization, weed/pest control, strategic trimming, and harvest coordination
             o     Learned basic management skills of farm laborers, various construction skills, including home construction, PVC piping and pumps, and the use of electrical generators

·        H&M Engineering, Inc. (Apr. 2011  May 2011)

o     Feasibility analysis for the US Trade & Development Agency on 2 different Hydroelectric projects in Latin America

·        Pont. Faculty of the Immac. Concep. (Sep. 2010 – Dec. 2010)

o     Performed front desk and security duties such as screening visitors, handing out badges, and answering calls

·        ViaSat, Inc.

o   Program Management (PM)

  § General project planning and coordination (e.g. resource management and customer liason)

  § Assisted in the creation of a few different ROMs, cost claims, and contract proposals

  § Developed detailed program schedules, including budgeting analysis, and tracked its progress using the Earned Value Management System

  § Participated in PM and Gate Reviews, made ETC adjustments, risk management, NPI and production management, CM/DM oversight, contracts oversight, QA oversight, business development, & lessons learned

  § Led a $1.1M project w/ most milestones and deliveries completed on time or early, while under budget by $200k

o   Lead

  § Conducted several different presentations: TIMs, DPT, Demo, FAT, TRR, PDR/CDR, DVT, and ATP support

  § Assisted in the identification, diagnosis, tracking, and reporting of project related sustaining and production issues (e.g. RMA processing, delivery schedules, and troubleshooting)

  § Led a few Engineers through design repairs & upgrades during the customer-integration phase of a program

  § Facilitated the technical information to the non-engineering departments (e.g. manufacturing, operations, configuration/data management, IS, security, administrative, purchasing, and quality assurance)

  § Led 2 other Engineers to develop a test equipment box for SPAWAR standards testing

  § Led a small team to develop an end-to-end encryption/decryption system using classified Tracking Telemetry & Control Encryption Algorithms on space qualified architecture FPGAs

o   Systems

  § Engineering analysis of top-level block diagrams and derivation of HW oriented requirements

o   Programmable Logic (PL)

  § Performed unit and system level testing of the front-end designs, including rigorous test benches

  § Performed the pin-layout, synthesis, mapping, placement, routing, and timing closure of the FPGAs

  § Assisted in the development of a PL Core Database for keeping track of in-house Intellectual Property

  § Experienced w/ with several different IP cores: GigE MAC, Type 1 Suite A (classified) & B (AES-GCM) encryption algorithms, GFP, ATM-UTOPIA, CAMs, HDLC, CTFF, EPB, NCO, SRAM ctrl’r, PLB, GPIO, UART, DCMs, embedded uProc’s, & other cores

  § Assisted in the development and test of several different FPGA designs on several different product platforms: experienced with Xilinx Virtex II, Xilinx Virtex II Pro, Altera Excalibur, Atmel AT6000, and a few CPLDs

o   Test

  § Performed extensive unit and system level testing of HW and firmware binaries (both PL and SW)

  § Assisted in the development and execution of functional test plans and procedures, leading to the customer acceptance for a few different programs

  § Oversaw the production testing, including acceptance test procedure writeup & training, of several units

  § High-speed network (UDP/TCP IPv4/v6 and ATM) testing using COTS traffic generator/analyzer

o   Hardware (HW)

  § Created a few dozen different BOMs, reference drawings, user manuals, build instructions, interfaced w/ mechanical engineers for proper assembly, & led buyers & planners through lead time & obsolescence issues

  § Assisted in the high/low level design, implementation, and testing of several boards for several different network security and related products

  § Assisted in design decisions and had a primary role in the schematic capture of the designs

  § CAD layout support, parts derating analysis (voltage & power), parts & PCB procurement support, chassis/drawer creation & modification, proper configuration & data management, up to 274 Mbps designs

·        Qualcomm CDMA Technologies (QCT)

o   Assisted in the design of a test-chip ASIC for the ARM11 processor, including the ETK and AHB blocks mentioned below, and successfully ran a validation test suite on the entire ARM11 processor

o   Constructed the Embedded Trace Kit (ETK) block using ARM’s reference design

  § Created this block’s High Level Design (HLD) document and successfully ran its validation test suite

  § Designed glue logic within this block including the addition of head switches for saving power [this hard macro was synthesized using all Low Voltage Threshold (LVT) cells], output voltage clamps, ATPG routing, a mux for JTAG TDO, a clock synchronizer, a spare parts kit, and ring oscillators

  § Performed initial pre-placed synthesis of the netlist using Design Compiler (DC), assisted in the placement, and assisted in the placed-gate netlist synthesis using Physical Compiler (PC)

o   Constructed and added glue logic for a 64 bit-wide AMBA High-Performance Bus (AHB) bus block

  § Implemented the bus sizers, bridges, decoders, slave-to-master muxes, and its arbiter

  § Designed and ran verification tests along with performing DC synthesis

·        University of California, San Diego

o   Ascertained the most optimal topology that could potentially be used in a packet-switched network on metal layers 6 and 7 of integrated circuits for multi-processor chips or any highly dense ASIC, thus eliminating interconnect cross-talk problems and on-chip busses

o   Created a Verilog simulator of 3 different network topologies: daisy chain, quad-tree, and hypercube

o   Ran several simulations under varied test vectors to determine the network topology that could withstand the highest capacity, deliver packets with lowest latency, and still be scalable in terms of area and number of hops

·        Hughes Network Systems

o   Performed the front-end design of a 33MHz 32bit Peripheral Component Interconnect (PCI) bus master controller, which interfaced with the ASIC’s backplane via the Open Core Protocol (OCP)

o   Designed a PCI bus arbiter and register array for command/control of the PCI block

o   Created a testbench with a varied set of tests to verify the functionality of the PCI sub-blocks I designed using Cadence's Signalscan and TransEDA's Verification Navigator

o   Stimulated my design using behavioral models of the backplane and a mock device on the PCI bus

o   Performed initial synthesis of colleague's and my own blocks using Synopsys’ DC tool

·        Hughes Network Systems

  o   Developed a Design Verification Test for an ASIC, including block diagrams, wiring diagrams, & a functional description of each block, & created a Low Level Design Document for testing of the PCI Bus Revision 2.2

·        Raytheon Systems Company

  o   Coded in C++ a simulator and an interactive GUI that was part of a large scale support equipment



SW Tools Experienced (Other): Agile, MPM, Excel’s BEST, Oracle, Ethereal, PUTTY, Microsoft Project, Microsoft Visio, Perforce, Microsoft’s Visual Source Safe, Merant Tracker, Frame Maker, and all Microsoft Office Tools

SW Tools Experienced (Programmable Logic Design): Atmel’s IDS, Modelsim, Xilinx’s Platform Studio, Xilinx's Project Navigator, Xilinx's Chip Scope Pro, Leonardo Spectrum, Xilinx's FPGA Layout Editor & Floorplanner, Xilinx's Impact, Synplicity’s Synplify, Xilinx’s XST, Synopsys' Design Compiler, Verilog, VHDL, Vi, Vim, QSIM2 (Qualcomm proprietary), Signalscan, Verification Navigator, Verilint, Tera Term Pro, and Sonics's Corecreator

SW Tools Experienced (Board): ORCAD Capture CIS, Xilinx’s PACE, Power PCB, Express SCH, Express PCB, Hyperlynx, and Mentor's Design Architect

SW Tools Experienced (Software Design): Unix, Cygwin, Pathfinder for ARM (not proficient), HaneWin’s DHCP Server, CDL API (ViaSat proprietary), XVI32, CVS, C++, C, Make, Tornado, Wind River's VxWorks, and PCMS

HW Tools Experienced: Logic Analyzer, Oscilloscope, Digital Multi-Meter, Power Supply, AX/4000 Traffic Generator/Analyzer, and CNI’s Nettest Fiber Optic Meter

SW Tools Educational: Ansoft's Harmonica, ADS, CADSYN, Nodal, Max+Plus II, PSpice, Matlab, Mathcad, HTML 4.0, Pascal, and Silver-Screen